About I²C

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09 August
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About I²C

I²C is a multi-master protocol that uses two signal lines. The two I²C signals are named ‘serial data’ (SDA) and ‘serial clock’ (SCL). There is no need of chip select (servant select) or compromise logic. Basically, any number of servants and any number of masters can be united onto these two signal lines and correspond to each other using a protocol that specifies:
 
7-bits servant addresses: every device united to the bus has got such a unique address;
certain control bits for governing the communication commence, end, and direct for any acknowledgement mechanism.
data are divided into 8-bit bytes
 
The data standard must be chosen betwixt 100 kbps, 400 kbps and 3.4 Mbps, accordingly called standard mode, a fast mode and high-speed mode. Some I²C variations contain 10 kbps and 1 Mbps as genuine speeds.
Physically, the I²C bus comprises the two active wires SDA and SCL and a ground connection. The effective wires are both bi-directional. The I2C protocol necessity states that the IC that begins a data transfer on the bus is treated the Bus Master. Therefore, at the time, all the other ICs were considered to be Bus Servants.
 
At electrical rank, there is literally no conflict at all if multiple instruments try to put any logic rank on the I²C bus lines together. If one of the drivers attempts to write a logical zero and the other a logical one, then the open-drain and pull-up arrangement ensure that there will be no shortcut and the bus will indeed see a logical zero transiting on the bus. In other words, in any conflict, a logic zero always ‘scores’.
Furthermore, the I²C protocol likewise helps at dealing with communication problems. Any apparatus present on the I²C listens to it permanently. Promising masters on the I²C encountering a START condition will wait until a STOP is encountered to attempt a new bus admission. Servants on the I²C bus will decode the device address that follows the START condition and checks if it doubles theirs. All the servants that are not addressed will wait until a STOP status is issued before listening repeatedly to the bus. Likewise, since the I²C protocol foresees active-low acknowledge bit after each byte, the master/servant couple can identify their counterpart presence. Ultimately, if anything else goes bad, this would signify that the apparatus ‘talking on the bus’ would know it by simply comparing what it sends with what is seen on the bus. If a difference is detected, a STOP case must be issued, which discharges the bus.

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